In many instances it can be necessary to implement hardware design verification methods and systems. The objective of design verification is to ensure that errors are absent from a design. Modern integrated circuit (IC) manufacturing technology is enabling IC designers to place millions of transistors on a single IC. Design complexity is doubling every 12–18 months, which causes design verification complexity to increase at an exponential rate. In addition, competitive pressures are putting increased demands on reducing time to market.
Today's design flow begins with a hardware specification document for the design. The engineer then implements the design in a language model, typically a Hardware Description Language (HDL). Such a model can be utilized to discover incorrect input/output (I/O) behavior through a stimulus in expected “results out” paradigm at the top level of the design.
By far the most popular method of functional verification today is simulation-based functional verification, which is widely utilized within the digital design industry as a technique for detecting defects within hardware designs. A very wide variety of products are available in the market to support simulation-based verification methodologies. However, a fundamental problem with conventional simulation-based verification approaches is that they are vector and test bench limited.
Simulation-based verification is driven by a test bench that explicitly generates the vectors to achieve stimulus coverage and also implements the checking mechanism. Test benches create a fundamental bottleneck in simulation-based functional verification. In order to verify a design hierarchy level, a test bench must be generated for it. This creates verification overhead for coding and debugging the test bench. Hence, a significant amount of expensive design and verification engineering resources are needed to produce results in a cumbersome and slow process.
Several methods have been attempted by Electronic Design Automation (EDA) companies today in order to address the shortcomings of simulation. However, none of these attempts address this fundamental limitation of the process. For example, simulation vendors have tried to meet the simulation throughput challenge by increasing the performance of hardware and software simulators thereby allowing designers to process a greater number of vectors in the same amount of simulation time. While this does increase stimulus coverage, the results are incremental. The technology is not keeping pace with the required growth rate and the verification processes are lagging in achieving the required stimulus coverage.
Formal verification is another class of tools that has entered the functional verification arena. These tools rely on mathematical analysis rather than simulation of the design. The strong selling point of formal verification is the fact that the results hold true for all possible input combinations to the design. However, in practice this high level of stimulus coverage has come at the cost of both error coverage and particularly usability. While some formal techniques are available, they are not widely used because they typically require the designer to know the details of how the tool works in order to operate it. Formal verification tools generally fall into two classes: (1) equivalence checking, and (2) model checking.
Equivalence checking is a form of formal verification that provides designers with the ability to perform RTL-to-gate and gate-to-gate comparisons of a design to determine if they are functionally equivalent. Importantly, however, equivalence checking is not a method of functional verification. Rather, equivalence checking merely provides an alternate solution for comparing a design representation to an original golden reference. It does not verify the functionality of the original golden reference for the design. Consequently, the original golden reference must be functionally verified using other methods.
Model checking is a functional verification technology that requires designers to formulate properties about the design's expected behavior. Each property is then checked against an exhaustive set of functional behaviors in the design. The limitation of this approach is that the designer is responsible for exactly specifying the set of properties to be verified. The property specification languages are new and obscure. Usually the technology runs into capacity problems and the designer has to engage with the tools to solve the problems.
There are severe limits on the size of the design and the scope of problems that can be analyzed. For example, the designer does not know which properties are necessary for complete analysis of the design. Further, specifying a large number of properties does not correlate well with better error coverage. Consequently, model checking has proven to be very difficult to use and has not provided much value in the verification process.
In view of the foregoing it would be desirable to create a verification methodology to create high quality designs and to increase the productiveness of design engineers by minimizing the tool setup effort and report processing effort. It is particular desirable to implement a method and system for hardware design verification, which is automatic in nature, and is tied directly to the original hardware design specification at the time of an actual hardware Power On Self Test (POST).